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2017 | Computing & IT
The Verilog language provides a means to model a digital system at many levels of abstraction from a logic gate to a complex digital system to a mainframe computer. The purpose of this book is to present the Verilog language together with a wide variety of examples so that the reader can gain a firm foundation in the design of the digital system using Verilog HDL. The different modeling constructs supported by Verilog are described in detail, and numerous examples and homework problems are included throughout.
Joseph Cavanagh
(Author)
| Published by | Taylor & Francis Ltd |
| Edition | Unknown |
| ISBN | 9781138099951 |
| Language | N/A |
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